Modelica.Electrical.Digital.Tristates

Transfergates, Buffers, Inverters, and WiredX

Information

Extends from Modelica.Icons.Package (Icon for standard packages).

Package Content

Name	Description
NXFERGATE	Transfergate with enable active high
NRXFERGATE	Transfergate with enable active high. Output strength reduced.
PXFERGATE	Transfergate with enable active low
PRXFERGATE	Transfergate with enable active low. Output strength reduced.
BUF3S	Tristate buffer with enable active high
BUF3SL	Tristate buffer with enable active low
INV3S	Tristate Inverter with enable active high
INV3SL	Tristate inverter with enable active low
WiredX	Wired node with multiple input and one output

Modelica.Electrical.Digital.Tristates.NXFERGATE

Transfergate with enable active high

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	DataOut
*	U	U
*	X	UX
*	0	Z
*	1	DataIn
*	Z	UX
*	W	UX
*	L	Z
*	H	DataIn
*	-	UX

  UX: if dataIn == U then U else X

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.NRXFERGATE

Transfergate with enable active high. Output strength reduced.

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	DataOut
*	U	U
*	X	UW
*	0	Z
*	1	DataIn, Strength Reduced
*	Z	UW
*	W	UW
*	L	Z
*	H	DataIn, Strength Reduced
*	-	UW

  UW: if dataIn == U then U else W
  Strength Reduced: 0 -> L, 1 -> H, X -> W

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.PXFERGATE

Transfergate with enable active low

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	DataOut
*	U	U
*	X	UX
*	0	DataIn
*	1	Z
*	Z	UX
*	W	UX
*	L	DataIn
*	H	Z
*	-	UX

  UX: if dataIn == U then U else X

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.PRXFERGATE

Transfergate with enable active low. Output strength reduced.

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table

DataIn	Enable	DataOut
*	U	U
*	X	UW
*	0	DataIn, Strength Reduced
*	1	Z
*	Z	UW
*	W	UW
*	L	DataIn, Strength Reduced
*	H	Z
*	-	UW

UW: if dataIn == U then U else W Strength Reduced: 0 -> L, 1 -> H, X -> W

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.BUF3S

Tristate buffer with enable active high

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Truth Table

DataIn	Enable	DataOut*
*	U	U
*	X	UX
*	0	Z
*	1	DataIn
*	Z	UX
*	W	UX
*	L	Z
*	H	DataIn
*	-	UX

  UX: if dataIn == U then U else X
  DataOut*: Strength map for DataOut according to tristate table Buf3sTable

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

strength output strength

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]
strength	output strength

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.BUF3SL

Tristate buffer with enable active low

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Truth Table

DataIn	Enable	DataOut*
*	U	U
*	X	UX
*	0	DataIn
*	1	Z
*	Z	UX
*	W	UX
*	L	DataIn
*	H	Z
*	-	UX

  UX: if dataIn == U then U else X
  DataOut*: Strength map for DataOut according to tristate table Buf3slTable

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

strength output strength

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]
strength	output strength

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.INV3S

Tristate Inverter with enable active high

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Truth Table

DataIn	Enable	DataOut*
*	U	U
*	X	UX
*	0	Z
*	1	Not DataIn
*	Z	UX
*	W	UX
*	L	Z
*	H	Not DataIn
*	-	UX

  UX: if dataIn == U then U else X
  DataOut*: Strength map for DataOut according to tristate table Buf3sTable

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

strength output strength

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]
strength	output strength

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.INV3SL

Tristate inverter with enable active low

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

and for tristate table http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Truth Table

DataIn	Enable	DataOut*
*	U	U
*	X	UX
*	0	Not DataIn
*	1	Z
*	Z	UX
*	W	UX
*	L	Not DataIn
*	H	Z
*	-	UX

  UX: if dataIn == U then U else X
  DataOut*: Strength map for DataOut according to tristate table Buf3slTable

Parameters

Name Description

tHL High->Low delay [s]

tLH Low->High delay [s]

strength output strength

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]
strength	output strength

Connectors

Name Description

enable

x

y

Name	Description
enable
x
y

Modelica.Electrical.Digital.Tristates.WiredX

Wired node with multiple input and one output

Information

Wires n input signals in one output signal, without delay.

Resolution table is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_misc.vhd

Extends from D.Interfaces.MISO (Multiple input - single output).

Parameters

Name Description

n Number of inputs

Name	Description
n	Number of inputs

Connectors

Name Description

x[n] Connector of Digital input signal vector

y Connector of Digital output signal

Name	Description
x[n]	Connector of Digital input signal vector
y	Connector of Digital output signal

Automatically generated Mon Sep 23 17:20:28 2013.