Modelica.Electrical.Digital.Memories

Information

Package Content

Name	Description
DLATRAM	Level sensitive Random Access Memory
DLATROM	Level sensitive Read Only Memory

Modelica.Electrical.Digital.Memories.DLATRAM

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active read enable RE:

Truth Table for high active write enable WE:

  *  = do not care
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U'
  Z  = L.'Z'

Simultaneous read/write operations are allowed. Firstly Write is carried out, then Read.

Parameters

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]
strength	output strength
n_addr	addr width
n_data	data width
table data definition
fileName

Connectors

Name	Description
RE	read enable
WE	write enable
addr[n_addr]	address
dataIn[n_data]	data input
dataOut[n_data]	data output

Modelica.Electrical.Digital.Memories.DLATROM

Information

Description in VHDL is given by http://www.cs.sfu.ca/~ggbaker/reference/std_logic/src/std_logic_entities.vhd

Truth Table for high active read enable RE:

  *  = do not care
  0  = L.'0' or L.'L'
  1  = L.'1' or L.'H'
  X  = L.'X' or L.'W' or L.'Z' or L.'-' or L.'U'
  Z  = L.'Z'

Parameters

Name	Description
tHL	High->Low delay [s]
tLH	Low->High delay [s]
strength	output strength
n_addr	addr width
n_data	data width
table data definition
fileName	File where matrix for memory is stored

Connectors

Name	Description
RE	read enable
addr[n_addr]	address
dataOut[n_data]	data output