Modelica.Electrical.Digital.Examples.Utilities

Information

This package contains utility components used by package Examples. Each component is built up hierarchically by components of the Gates package. In this way the Gates components were tested, and their usage is demonstrated.

Package Content

Name	Description
MUX4	4 to 1 Bit Multiplexer
RS	Unclocked RS FlipFlop
RSFF	Unclocked RS FlipFlop
DFF	D FlipFlop
JKFF	JK FlipFlop
HalfAdder	Half adder
FullAdder	Adding circuit for binary numbers with input carry bit
Adder	Generic N Bit Adder
Counter3	3 Bit Counter
Counter	Generic N Bit Counter

Modelica.Electrical.Digital.Examples.Utilities.MUX4

Information

MUX4 is a four bit multiplexer which is built up by And, Not, and Or gates according to the schematic.

The parameters delayTime and q0 are prepared but not yet used in the component. The MUX4 component uses standard values in its components.

Parameters

Name	Description
delayTime	Delay time [s]
q0	Initial value

Connectors

Name	Description
d0
d1
d2
d3
a0
a1
d

Modelica.Electrical.Digital.Examples.Utilities.RS

Information

RS is a basic component for e.g., the RS (set-reset) flipflop, which is built up by Nor gates according to the schematic. To avoid a numerical loop a small transport delay is inserted which delay time is a parameter of the RS component. Also its initial value can be set by parameter.

Parameters

Name	Description
delayTime	Delay time [s]
q0	Initial value of output

Connectors

Name	Description
s
r
q
qn

Modelica.Electrical.Digital.Examples.Utilities.RSFF

Information

Basing on the RS component RSFF is a RS (set-reset) flipflop composed according the schematic. Its parameter delayTime is the delay time of the RS component transport delay, q0 is the initial value of that delay.

Parameters

Name	Description
delayTime	Delay time [s]
q0	Initial value

Connectors

Name	Description
s
r
q
qn	not Q
clk

Modelica.Electrical.Digital.Examples.Utilities.DFF

Information

Basing on the RS component DFF is a D flipflop composed according the schematic. Its parameter delayTime is the delay time of the RS component transport delay, q0 is the initial value of that delay.

Parameters

Name	Description
Tdel	Delay time [s]
QInit	Initial value

Connectors

Name	Description
d
q
qn	not Q
clk

Modelica.Electrical.Digital.Examples.Utilities.JKFF

Information

Basing on the RS component JKFF is a J-K-flipflop composed according the schematic. Its parameter delayTime is the delay time of the RS component transport delay, q0 is the initial value of that delay.

Parameters

Name	Description
delayTime	Delay time [s]
q0	Initial value

Connectors

Name	Description
j
q
qn	not Q
clk
k

Modelica.Electrical.Digital.Examples.Utilities.HalfAdder

Information

HalfAdder is a two bit adder which is composed by Gates components.

Its logic behavior is like this:

HalfAdder behavior

The parameter delayTime is the delay time (tLH=tHL) of both the components.

Parameters

Name	Description
delayTime	Delay time

Connectors

Name	Description
b
s
a
c

Modelica.Electrical.Digital.Examples.Utilities.FullAdder

Information

FullAdder is a two bit adder with additional carry in bit which is composed by Gates components.

Its logic behavior is like this:

FullAdder behavior

Connectors

Name	Description
a
b
c_in
s
c_out

Modelica.Electrical.Digital.Examples.Utilities.Adder

Information

The Adder is a generic n bit adder which is composed as a chain of FullAdder components. n can be chosen by the user, a and b are the n bit input vectors, s is the sum vector, and c_out is the carry bit of the "highes" FullAdder. All components are built up by Gate components.

Parameters

Name	Description
n	Number of single adders

Connectors

Name	Description
a[n]
b[n]
c_in
s[n]
c_out

Modelica.Electrical.Digital.Examples.Utilities.Counter3

Information

The Counter3 counts the high-low slopes of the count signal, if the enable signal is set to be true. It is composed by three JK flipflops. q0, q1, and q2 are the bits of the resulting number, where q0 is the lowest, and q2 the highest bit.

Connectors

Name	Description
enable
q2
count
q1
q0

Modelica.Electrical.Digital.Examples.Utilities.Counter

Information

The Counter is a generic component, which counts the high-low slopes of the count signal, if the enable signal is set to be true. It is composed by n JK flipflops. q is the resulting number, where q[0] is the lowest, and q[n] the highest bit.

Parameters

Name	Description
n	Number of bits
delayTime	Delay of each JKFF [s]
q0	Initial value

Connectors

Name	Description
enable
count
q[n]